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nikhilnh924's avatar
nikhilnh924
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3 years ago

Altera on chip IP core simulation model errors due to generated encrypted files from quartus.

Hello everyone.

I have generated the on-chip flash IP core simulation model files in VHDL using Quartus prime lite v18.1. I use this generated VHDL and msim_tcl script file for simulation using the ModelSim. The script results in the error stating that there are some protected variables. I know that this is due to the encryption of simulation files. However, I learned that it would be able to run these encrypted files using ModelSim.

The warning message is shown below:

** Warning: (vsim-3017) ./../submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Too few port connections. Expected 11, found 6.
# Time: 0 ps Iteration: 0 Instance: /boc_flash/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: C:/intelfpga_lite/21.1/quartus/eda/sim_lib/220model.v
# ** Warning: (vsim-3722) ./../submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'shiftin'.
# ** Warning: (vsim-3722) ./../submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'aset'.
# ** Warning: (vsim-3722) ./../submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ./../submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ./../submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'q'.
# ** Warning: (vsim-3017) ./../submodules/altera_onchip_flash.v(302): [TFMPC] - Too few port connections. Expected 18, found 17.
# Time: 0 ps Iteration: 0 Instance: /boc_flash/onchip_flash_0/altera_onchip_flash_block File: C:/intelfpga_lite/21.1/quartus/eda/sim_lib/fiftyfivenm_atoms.v
# ** Warning: (vsim-3722) ./../submodules/altera_onchip_flash.v(302): [TFMPC] - Missing connection for port 'bgpbusy'.
# ** Warning: (vsim-3017) <protected>(<protected>): [TFMPC] - Too few port connections. Expected <protected>, found <protected>.
# Time: 0 ps Iteration: 0 Protected: /boc_flash/onchip_flash_0/altera_onchip_flash_block/inst/<protected>/<protected>/<protected>/<protected>/<protected> File: nofile
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3015) <protected>(<protected>): [PCDPC] - Port size (<protected>) does not match connection size (<protected>) for <protected>.<protected>
# Time: 0 ps Iteration: 0 Protected: /boc_flash/onchip_flash_0/altera_onchip_flash_block/inst/<protected>/<pr

The compilation of the design is complete but the simulation stops in the elaboration stage.

I have also looked into few forum threads ( https://community.intel.com/t5/FPGA-Intellectual-Property/Modelsim-error-on-altera-onchip-flash-block-Error-vsim-3033/td-p/681146/ ) for solution but did not work. So It would be good to get any help on this.

Thanks
Nikhil

6 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    Do you mind to attach the project .qar file for us to replicate the warnings and investigate further?


    Thanks.


    • nikhilnh924's avatar
      nikhilnh924
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hello tventing,

      I am sorry, I cannot attach my project.qar file due to company policies. But I can provide you with more details about the project. we have a BOC (backplane operation controller) system to control a series of 16 PCI slots and the FPGA max 10 with internal flash is used. The configuration is stored in the flash and this configuration is loaded once powered. I have integrated the generated flash module and simulated model in our design to test it. When I compile the Altera libraries with this flash I encounter this protected issue and the elaboration fails in Modelsim. The warnings and error messages are shown below:

      # ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'shiftin'.
      # Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
      # ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'aset'.
      # Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
      # ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'sclr'.
      # Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
      # ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'sset'.
      # Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
      # ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'q'.
      # Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
      # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'altera_onchip_flash_block'. Expected 18, found 17.
      # Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/altera_onchip_flash_block File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash.v Line: 302
      # ** Warning: (vsim-3722) ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash.v(302): [TFMPC] - Missing connection for port '<protected>'.
      # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '<protected>'. Expected <protected>, found <protected>.
      # Time: 0 ps Iteration: 0 Protected: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/altera_onchip_flash_block/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: ./../vendor/altera/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38
      # ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
      # ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
      # ** Warning: (vsim-3015) [PCDPC] - Port size (<protected>) does not match connection size (<protected>) for <protected>.<protected>
      # Time: 0 ps Iteration: 0 Protected: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/altera_onchip_flash_block/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: ./../vendor/altera/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38
      # ** Fatal: (SIGSEGV) Bad handle or reference.
      # Time: 0 ps Iteration: 0 Instance: /tb_top File: ./tb_top_iocm5_12slot.vhd Line: UNKNOWN
      # FATAL ERROR while loading design
      # Error loading design
      # Error: Error loading design
      # Pausing macro execution
      # MACRO ./all.do PAUSED at line 21

      Attaching the on-chip flash IP Core parameters for more references. let me know if you need more information on this.

      Thanks
      Nikhil

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    Since you couldn't provide the project file, it's difficult to debug the errors. For my end, I have tried a design example of MAX10 that utilizes on-chip flash IP. I managed to successfully simulate the design in Modelsim.


    Steps to simulate in Modelsim:

    1. Open Modelsim (not from Quartus RTL Simulation)
    2. Cd to msim_setup.tcl file directory
    3. do msim_setup.tcl
    4. ld
    5. run 100ns (to see the waveform)


    Attached the design example .qar file. You may try it out and view the port connection. Let me know if the design example helps.


    Thanks.

    Best Regards,

    Ven Ting


  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    May I know any updates on this?


    Thanks.

    Best Regards,

    Ven Ting


  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thanks.

    Best Regards,

    Ven Ting


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey