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nikhilnh924's avatar
nikhilnh924
Icon for New Contributor rankNew Contributor
3 years ago

Altera on chip IP core simulation model errors due to generated encrypted files from quartus.

Hello everyone. I have generated the on-chip flash IP core simulation model files in VHDL using Quartus prime lite v18.1. I use this generated VHDL and msim_tcl script file for simulation using th...
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


Since you couldn't provide the project file, it's difficult to debug the errors. For my end, I have tried a design example of MAX10 that utilizes on-chip flash IP. I managed to successfully simulate the design in Modelsim.


Steps to simulate in Modelsim:

  1. Open Modelsim (not from Quartus RTL Simulation)
  2. Cd to msim_setup.tcl file directory
  3. do msim_setup.tcl
  4. ld
  5. run 100ns (to see the waveform)


Attached the design example .qar file. You may try it out and view the port connection. Let me know if the design example helps.


Thanks.

Best Regards,

Ven Ting