Altera on chip IP core simulation model errors due to generated encrypted files from quartus.

Hello tventing,

I am sorry, I cannot attach my project.qar file due to company policies. But I can provide you with more details about the project. we have a BOC (backplane operation controller) system to control a series of 16 PCI slots and the FPGA max 10 with internal flash is used. The configuration is stored in the flash and this configuration is loaded once powered. I have integrated the generated flash module and simulated model in our design to test it. When I compile the Altera libraries with this flash I encounter this protected issue and the elaboration fails in Modelsim. The warnings and error messages are shown below:

# ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'shiftin'.
# Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
# ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'aset'.
# Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
# ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'sclr'.
# Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
# ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'sset'.
# Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
# ** Warning: (vsim-8822) [TFMPC] - Missing Verilog connection for formal VHDL port 'q'.
# Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1167
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'altera_onchip_flash_block'. Expected 18, found 17.
# Time: 0 ps Iteration: 0 Instance: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/altera_onchip_flash_block File: ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash.v Line: 302
# ** Warning: (vsim-3722) ./../vendor/boc_flash/simulation/submodules/altera_onchip_flash.v(302): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '<protected>'. Expected <protected>, found <protected>.
# Time: 0 ps Iteration: 0 Protected: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/altera_onchip_flash_block/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: ./../vendor/altera/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3015) [PCDPC] - Port size (<protected>) does not match connection size (<protected>) for <protected>.<protected>
# Time: 0 ps Iteration: 0 Protected: /tb_top/dut/efs1/boc_flash_inst/onchip_flash_0/altera_onchip_flash_block/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: ./../vendor/altera/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ./tb_top_iocm5_12slot.vhd Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./all.do PAUSED at line 21

Attaching the on-chip flash IP Core parameters for more references. let me know if you need more information on this.

Thanks
Nikhil