Forum Discussion
nikhilnh924
New Contributor
3 years agoAltera on chip IP core simulation model errors due to generated encrypted files from quartus.
Hello everyone. I have generated the on-chip flash IP core simulation model files in VHDL using Quartus prime lite v18.1. I use this generated VHDL and msim_tcl script file for simulation using th...
VenT_Altera
Frequent Contributor
3 years agoHi,
As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thanks.
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Ven Ting
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