altera gmii to sgmii ip timing problem

You can take a look in this design, rewrite the sdc according to this design and see if you can meet the timing. Let me know how it goes.

You will also need to take a look at:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf

page 183 although this is A10, It should be apply to all device.

Basically, it mention that you need a different IO standards if your frequencies running too high.

any update?

Hi,

Rewriting the SDC according to the cv_soc_rgmii_5csxfc6 design didn't help me.

I attached an archive of the project, can you please help me with this timing issue?

(The project qpf is under fpga/synth/evb3022_synth)

Thanks,

I get a lot of error when try to compile the project

Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/mutex_2_h2f_nios_0.ip.

Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/nios_qsys_timer_0.ip.

Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/mutex_3_to_h2f_bridge_0.ip.

Can you make sure that your ip directory zip down all the necessary files?

Hi,

I added some files. please try the attached ZIP:

Thanks,

Thanks, I manage to run the full compilation on your design.

Did you follow the constrain provided in cv_soc_rgmii_5csxfc6.qar files? As I compare the sdc that you have written, there are some missing clock like the create_generated clock which is use of the switch.

Can you review your sdc again and match with the example above?

any update?