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16 years ago

Altera FFT simulation

I'm working with Altera streaming 256 point FFT core. I've discovered the errata on the core (V9) rearding mismatch between the Matlab sims and HDL sims and the limit on the input range.

Looking at the FFT User Guide, it tells me that the sink_valid signal must be asserted for the source valid to be asserted (and a valid data output). It also says that the sink_sop and sink_eop must be driven while extracting the final frames of data even if no further valid input data is being supplied.

If I run the Verilog testbench that is generated by the core generator, I see that the above conditions are not met yet the core puts out correct data.

Anybody else run into this? How are others driving the inputs while pulling out the delayed FFT results?

Thanks for any input on this.

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