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Altera_Forum
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15 years ago

altera_avalon_dc_fifo only availabe in Verilog

Hi,

I have a design here that I want to simulate. I only have a VHDL simulation license and now I found out there are three Verilog source files included that were supplied by Altera. I want to replace these files with VHDL counterparts (at least for the simulation process, for synthesis I could keep the old files). The files names are:

altera_avalon_dc_fifo.v

altera_synchronizer.v

altera_synchronizer_bundle.v

they are part of the sopc_builder_ip. Did I miss installing the VHDL version, too? If there is no VHDL version, what is the recommended way to get the design simulated without having to pay many, many euros for a mixed simulation license?

Best regards,

flintstone

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Ok, meanwhile I managed to synthesize the Verilog module to a VHDL netlist. Pityfully there is a problem with different port sizes in the entity synthesized.

    Maybe somebody got experience with this?

    Regards,

    Matthias