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Altera_Forum
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15 years ago

altera_avalon_dc_fifo only availabe in Verilog

Hi, I have a design here that I want to simulate. I only have a VHDL simulation license and now I found out there are three Verilog source files included that were supplied by Altera. I want to...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Ok, meanwhile I managed to synthesize the Verilog module to a VHDL netlist. Pityfully there is a problem with different port sizes in the entity synthesized.

Maybe somebody got experience with this?

Regards,

Matthias