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vikas194's avatar
vikas194
Icon for New Contributor rankNew Contributor
3 years ago

ALT LVDS RX IP does not support Frame clock ?

Hello,

we are designing a LVDS receiver on Cyclone 10 LP which receives differential data from TI AWR6843 . We have 3 ports from AWR6843 that is

1. Differential data out,

2. Differential clock out

3. Differential frame clock.

These ports are not compatible with ALT LVDS RX IP.

TI AWR6843 has 4 channel ADC with 16 bits per sample which is given out through 2 lanes

at 600Mbps (300 MHz).

There is no input port available for frame clock. Is their any option available to implement LVDS receiver with frame clock? . Also what should be the pin mapping for this frame clock? .

Can you please specify what should be the PLL configurations to implement both bit clock & frame clock in a ALT LVDS receiver

Thanks & regards

vikas R

5 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hello,

    quite obviously, a PLL can only have one input clock. A PLL operated LVDS receiver will typically only use the frame clock and generate the bit clock internally.

    Regards

    Frank

  • vikas194's avatar
    vikas194
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello frank, thanks for replying
    Since we are using only frame clock, is it okay to discard bit clock (differential clock out from AWR6843)? if not, how can this clock be used?

    Also I wanted to know how rx_channel_data_align input has to be generated with respect to frame clock, since we don't have this logic in TI AWR6843 LVDS TX.

    regards

    Vikas

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hello,

    please consider that I'm not familiar with the interface details of AWR6843.

    In those cases where the frame clock corresponds to transmitted word boundary, you don't necessarily need the data align feature, just adjust the PLL slow clock phase so that you get the output right. That's at least what I'm doing with ADC LVDS interfaces.

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

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