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vikas194
New Contributor
New ContributorALT LVDS RX IP does not support Frame clock ?
Hello,
we are designing a LVDS receiver on Cyclone 10 LP which receives differential data from TI AWR6843 . We have 3 ports from AWR6843 that is
1. Differential data out,
2. Differential clock...
FvM
Super Contributor
Super ContributorHello,
please consider that I'm not familiar with the interface details of AWR6843.
In those cases where the frame clock corresponds to transmitted word boundary, you don't necessarily need the data align feature, just adjust the PLL slow clock phase so that you get the output right. That's at least what I'm doing with ADC LVDS interfaces.
