Forum Discussion

vikas194's avatar
vikas194
Icon for New Contributor rankNew Contributor
3 years ago

ALT LVDS RX IP does not support Frame clock ?

Hello, we are designing a LVDS receiver on Cyclone 10 LP which receives differential data from TI AWR6843 . We have 3 ports from AWR6843 that is 1. Differential data out, 2. Differential clock...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hello,

quite obviously, a PLL can only have one input clock. A PLL operated LVDS receiver will typically only use the frame clock and generate the bit clock internally.

Regards

Frank