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vikas194
New Contributor
New ContributorALT LVDS RX IP does not support Frame clock ?
Hello,
we are designing a LVDS receiver on Cyclone 10 LP which receives differential data from TI AWR6843 . We have 3 ports from AWR6843 that is
1. Differential data out,
2. Differential clock...
FvM
Super Contributor
Super ContributorHello,
quite obviously, a PLL can only have one input clock. A PLL operated LVDS receiver will typically only use the frame clock and generate the bit clock internally.
Regards
Frank
