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Altera_Forum's avatar
Altera_Forum
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17 years ago

alt_ddio_in puzzles inside Deserializer

hi, gals and guys, in recent days, i am working on a deserializer to interface with a high speed ADC. It's a 12-bit, DDR interface, with bit clock running @240 MHz. I use the alt_ddio_in to construct this deserializer. For this ddio register, i prepared two simulations with modelsim: netlist without of sdf file, and netlist with sdf file. After a carefully comparison of these two waveforms, i found the alt_ddio_in is not working as expected: the input_cell_h register lost some bits. For detailed information, you can refer to the attached image.

Facing with this, i am really puzzled, i don't know where to go for the right answer. anyone has the related experience for such filed?

have a nice day,

regards,

eric

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    From the bitmap,I can't see which clock is actually used for the DDIO register. But the result suggests that setup- or hold times are violated.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    hi, FvM, the tx_dco is used to latch the ddio_in register, and tx_dat is connected to the datain of the ddio_in register. The relationship between them is center-aligned. I compared the input_cell_h register inside the ddio_in with post-map netlist and post-fit netlist, i found that the input_cell_h has missed up some data, besides the shifted behavior. While for the input_cell_l, the difference between post-map one and post-fit one only confines to the shifted property. any suggestions?

    best regards,

    eric
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I wonder if the said clock alignment exists at the DDIO input register. Did you use the timing analyzer to verify the timing?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    hi, FvM, yea, i think you are right. After several day's work, i got an somehow acceptable solution for this. I found that the 240 MHz requirement is a little higher for the DDIO_IN registers inside ep2c35c8 device. I made two tests to verify this idea. Firstly, i decrease the launch clock to 180 MHz, i found that the ddio_in register worked fine. And then i migrated this design into ep2c35c6, even the 240 MHz was working. So this answers my question.

    thanks for ur helpful suggestions, FvM.

    regards,

    eric