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Altera_Forum
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18 years ago

alt_ddio_in puzzles inside Deserializer

hi, gals and guys, in recent days, i am working on a deserializer to interface with a high speed ADC. It's a 12-bit, DDR interface, with bit clock running @240 MHz. I use the alt_ddio_in to construct...
Altera_Forum's avatar
Altera_Forum
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18 years ago

hi, FvM, the tx_dco is used to latch the ddio_in register, and tx_dat is connected to the datain of the ddio_in register. The relationship between them is center-aligned. I compared the input_cell_h register inside the ddio_in with post-map netlist and post-fit netlist, i found that the input_cell_h has missed up some data, besides the shifted behavior. While for the input_cell_l, the difference between post-map one and post-fit one only confines to the shifted property. any suggestions?

best regards,

eric