Alt_asmi

They had me modify the file epcs_asmi.v lines as follows:

original code:

initial

ncs_reg = 0;

// synopsys translate_on

always @ ( negedge clkin_wire or posedge end_ophdly)

if (end_ophdly == 1'b1) ncs_reg <= 1'b0;

else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b1;

modify it to:

initial

ncs_reg =1;

// synopsys translate_on

always @ ( negedge clkin_wire or posedge end_ophdly)

if (end_ophdly == 1'b1) ncs_reg <= 1'b1;

else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b0;

Of course YMMV. But I'd be really surprised if CycII had the same issue, that's a relatively mature product. But then things get broken with every new release so I guess it may not be that hard to beleive.

I use:

1. Quartus 8 + SP1

2. Cyclone III

3. EPCS64

4. Verilog

If using the mega wizard as is, and it have major bug, the CSn line to the EPCS64 is active hi and should be active low.

I found manual correction in altera forum

http://www.alteraforum.com/forum/archive/index.php?t-1141.html (http://www.alteraforum.com/forum/archive/index.php?t-1141.html)

johns

April 9th, 2008, 10:50 AM

They had me modify the file epcs_asmi.v lines as follows:

original code:

initial

ncs_reg = 0;

// synopsys translate_on

always @ ( negedge clkin_wire or posedge end_ophdly)

if (end_ophdly == 1'b1) ncs_reg <= 1'b0;

else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b1;

modify it to:

initial

ncs_reg =1;

// synopsys translate_on

always @ ( negedge clkin_wire or posedge end_ophdly)

if (end_ophdly == 1'b1) ncs_reg <= 1'b1;

else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b0;

Manually change the verilog file This fix the issue, but still one major issue:

The pin DCLK to EPCS64 is always active; this core should turn ON the clock only after try to access to the EPCS64 and not all the time (power issue, EMI/RFI issues)

Please send me quick correction to this issue as well

This issue has been fixed in QII 9.0.

But the manual does not document that "Device and Pin Options" -> "Dual-Purpose pins" must all be set to "Use as regular I/O" otherwise the communication to the EPCS is not established. That is omission in the manual is IMHO a bug.

--- Quote Start ---

the only possibility allowed in the drop down box for the ADS0, nCS0 pins is "As input tri-stated"

--- Quote End ---

Yes, this seems to be a Quartus "special" with Cyclone II. The Altera SFL MegaFunction is however working correctly with exactly this setting, obviously using ASDO, NCSO and DCLK as output in user mode. So I would expect altasmi to work as well, despite of this setting.

Another option is to set PS configuration in Quartus, but actually configure AS with MSEL. Then you get free choose of dual-purpose pin configuration again. I didn't try with Cyclone II, but I needed this workaround with Cyclone III due to some oddities of previous Quartus versions.