Alt_asmi

I use:

1. Quartus 8 + SP1

2. Cyclone III

3. EPCS64

4. Verilog

If using the mega wizard as is, and it have major bug, the CSn line to the EPCS64 is active hi and should be active low.

I found manual correction in altera forum

http://www.alteraforum.com/forum/archive/index.php?t-1141.html (http://www.alteraforum.com/forum/archive/index.php?t-1141.html)

johns

April 9th, 2008, 10:50 AM

They had me modify the file epcs_asmi.v lines as follows:

original code:

initial

ncs_reg = 0;

// synopsys translate_on

always @ ( negedge clkin_wire or posedge end_ophdly)

if (end_ophdly == 1'b1) ncs_reg <= 1'b0;

else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b1;

modify it to:

initial

ncs_reg =1;

// synopsys translate_on

always @ ( negedge clkin_wire or posedge end_ophdly)

if (end_ophdly == 1'b1) ncs_reg <= 1'b1;

else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b0;

Manually change the verilog file This fix the issue, but still one major issue:

The pin DCLK to EPCS64 is always active; this core should turn ON the clock only after try to access to the EPCS64 and not all the time (power issue, EMI/RFI issues)

Please send me quick correction to this issue as well