Agilex5 add own IP fails in RiscFree

It seems all attempts to add own IP cores fail when accessed from NIOS-V

We did simplesrt possible IP core:

module pio (
input wire reset_rst, // reset.reset
input wire [3:0] avl_mem_address, // word adressing two address bits less
input wire avl_mem_read, // .read
output wire [31:0] avl_mem_readdata, // .readdata
output wire avl_mem_readdatavalid, // .readdatavalid
input wire avl_mem_write, // .write
input wire [31:0] avl_mem_writedata, // .writedata
input wire [3:0] avl_mem_byteenable, // .byteenable
output wire avl_mem_waitrequest, // .waitrequest
input wire avl_clock // avl_clock.clk
);

assign avl_mem_waitrequest = 1'b0; // we are ready always
assign avl_mem_readdatavalid = 1'b1;
assign avl_mem_readdata = 32'h12345678;

endmodule

But this also fails, when we open memory browser to look at the memory range assigned we get:

[0x800000] Internal error. Abstract command execution failed: An abstract command is currently being executed.

We tried with one 3rd party IP core in VHDL with the same error!

So what is happening and what can be the problem? Adding IP cores from Altera catalog works well.