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AnttiLukats's avatar
AnttiLukats
Icon for Occasional Contributor rankOccasional Contributor
10 months ago
Solved

Agilex5 add own IP fails in RiscFree

It seems all attempts to add own IP cores fail when accessed from NIOS-V We did simplesrt possible IP core: module pio ( input wire reset_rst, // reset.reset input wire [3:0] avl_mem_address, // ...
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  • AnttiLukats's avatar
    AnttiLukats
    10 months ago

    I fixed the problem by removing readdatavalid signals. Now it works in RiscFree. So it was a problem with the IP core.

    It seems the new version of the tools are very strict about Avalon protocol.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
10 months ago

A number of things.

First of all, are you creating this as a custom component in Platform Designer? How are you connecting it to the processor?

All data transfers in Platform Designer must be synchronous using the clock. Doing an "assign" like what you've done, there's nothing for the processor to read.