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AnttiLukats's avatar
AnttiLukats
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Agilex5 add own IP fails in RiscFree

It seems all attempts to add own IP cores fail when accessed from NIOS-V We did simplesrt possible IP core: module pio ( input wire reset_rst, // reset.reset input wire [3:0] avl_mem_address, // ...
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  • AnttiLukats's avatar
    AnttiLukats
    1 year ago

    I fixed the problem by removing readdatavalid signals. Now it works in RiscFree. So it was a problem with the IP core.

    It seems the new version of the tools are very strict about Avalon protocol.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


I’m glad that your question has been addressed, I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Regards

Jingyang, Teh