Hi Dexter22 ,
Based on the your provided result
- Yes — in PIPE Direct mode on Agilex 7 R‑Tile, the hard IP intentionally bypasses PCS word/symbol alignment. You will see raw, unaligned serialized data on the PIPE RX interface.
- Yes — you are responsible for soft word alignment (comma/K28.5 detection with bitslip), bit orientation handling (bit‑reversal if needed), and subsequent 8b/10b or 128b/130b processing in the FPGA fabric.
- No — there is no IP parameter to turn on hard PCS alignment while retaining PIPE Direct. If you want hard alignment and decoding, you must use the standard PCIe controller modes (not PIPE Direct).
As PIPE Direct Mode is mostly customize by user (no available design example provided by Altera), I would lay down some of debug suggestion based on my experience, hope that can help you to move a step forward.
Verify bit ordering:
- If your K28.5 only appears after reversing the 10 bits, your lane is likely bit‑reversed relative to your decoder.
- Make the reversal a parameter so you can flip per lane without re‑synthesis.
Implement a robust comma detector:
- Check for both 0011111010 (RD−) and 1100000101 (RD+) across all bit positions of your capture word.
- Once aligned, validate with running disparity and known training patterns (TS1/TS2) to confirm stability.
Confirm your valid‑bit placement:
- At Gen1/Gen2 speeds, only certain bits of the RX bus are meaningful per cycle (commonly the 10 LSBs of each half). Treat upper bits as don’t‑care until alignment is achieved.
Use training patterns as a sanity check:
- The repeated 0x155 (D10.2) is expected in TS1 fields. Once aligned, you should cleanly parse TS1/TS2 content and comma locations.
Regards,
Wincent
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