Agilex 5 Reset Sequencer - Design Assitant reports IPC-40038 violation

Hi,

I am using 2x25Gbit PCS/PMA function only (with FEC) and 2x10Gbit PCS/PMA function only (without FEC) in my Agilex 5 design (device A5ED043AB32AE3V, Quartus Pro 26.1). 25Gbit transceiver are using IO bank 4C while 10Gbit transceivers are using IO bank 1C

There is one reference clock driving the GTS PLL as well as the PMA reference clock input of the Ethernet IP core for both the 25Gbit interface and the 10Gbit interface. They are located in the IO bank of their transceivers.

There is one Reset Sequencer for 25Gbit and 10Gbit each. Quartus compiles the design without errors but the Design Assitant reports a Critical Error "IPC-40038 - Individual bit of Control Unit clock of Reset Sequencer IP can drive only a single instance of Ethernet or PCIE IP"

Basically I followed the Use Case 1 chapter 5.6.1 of the GTS Transceiver PHY User Guide version 2026.03.13. Both PCS/PMA units of each type receive the same o_pma_cu_clk from their Reset Sequencer. In a Quad there is just one or two Ethernet Hard IPs but there are 4 PCS/PMA functions accordig to the same document. Can I safely ignore this Critical Warning, is the Warning wrong or do I miss something?

Thank you

Gerhard