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Phix33's avatar
Phix33
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23 days ago

Agilex 5 EMIF-LPDDR4, AXI4 Read-Write Starvation Issue

Hello, I have a Agilex 5 design (based on the Terasic DE25_Nano) implementing the LPDDR4-EMIF.

My own IP (acting as a AXI4 Manager) is connected to the AXI4 Subordinate port of the EMIF to read and write onto the LPDDR.

All is working perfectly, but in some R/W pattern cases where the write channel issues many consecutive commands, the Read channel is starved until the end of the write sequence of commands, which means no valid data are received before a very long (unacceptable) time.

Obviously the EMIF gives the priority to the write channel which lead to read starvation.

Regarding the EMIF Parameters Settings, I tested the three "Controller Performance Profiles" without any success. I also tested several set of values for the "Data Bus Turnaround Times" settings without any success too.

Ideally, I would expect either disabling Reordering or configuring a Starvation counter limit, but these parameters do not exist in the Agilex 5 EMIF IP. As a remark, I noticed these settings (Enable Reordering + Starvation limit) exist in the Agilex 7 EMIF IP.

Regarding the External Memory Interfaces (EMIF) IP User Guide for Agilex 5 FPGAs and SoCs, section "Features of the Agilex 5 Hard Memory Controller" Table 30, I noticed there is a parameter named "Starvation counter" but there is no explanation how to configure it.

In summary, I do not see any way to have control over Reordering/Starvation with Agilex 5 EMIF-LPDDR4.

Thank you in advance for any suggestion. Regards

Memory

3 Replies

  • yoichiK_altera's avatar
    yoichiK_altera
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    23 days ago

    Agilex5 EMIF IP controller tries to maximize the efficiency based on coming traffic data pattern and user can not control starvation and reordering option.  Thus in that your case completing the sequential write command then read command is processed.   You may want to order write and read command separately at AXi bus interface ie issue read command after write command .   

    • Phix33's avatar
      Phix33
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      23 days ago

      Thank you yoichiK for your prompt reply,

      So you confirm that Reordering and Starvation cannot be controlled !!!

      For me it is a big problem because the host driving the AXI Write channel (the Writer) is fully independent from the host driving the AXI Read channel (the Reader). Moreover, the Reader cannot accept starvation because it drives a video sub-system with determinism and low-latency requirement.

      By the way, it is not consistent/rational to handle reordering at EMIF side for effficiency reason and to ask my Reader to wait until the end of the Writer sequence.

      Please, find below the Signal-Tap of the EMIF AXI4 R/W interface. On the below pattern, the Writer fully monopolizes the DDR during hundreds of commands (AWVALID/AWREADY). The Reader issue a few commands (ARVALID/ARREADY) then it waits for the data (RVALID) during around 2000 cycles (after the Writer stops), which is not acceptable.

      In this use case, the only solution would be to stop the Writer each time the Reader issue a command, which leads to kill the overall efficiency...

      If there is no workaround to control priority/reordering/starvation, I would be forced to conclude the Agilex 5 EMIF is not compatible with my need.

      Thank you in advance if you have any suggestion...

      • yoichiK_altera's avatar
        yoichiK_altera
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        21 days ago

        I tried to replicate the issue at my side with Agilex5E devkit.  and did similar data traffic on hardware.

        I use async mode at AXI interface and burst length is 2 with consecutive write access.  During consecutive write access one read access is issued and I see rvalid is returned before completion of consecutive write access.