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Aleh_TS's avatar
Aleh_TS
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3 days ago

Agilex 5 dual simplex fitting

Hello all.

In my project I have to implement HDMI input and HDMI output.

As a starting point I took an example design, which is generated from HDMI IP core.

This example uses the dual simplex to place input and output to the same transciever block (bank 4C).

By default the rx component has an offfset 1 in dual simplex group:

Do not pay attention to the second DS_Group, it is not used in the code.

This project can be successfully compiled.

I work with quartus 25.1 Pro.

Due to some reasons, this dual simplex configuration is not suitable for my project. I need rx offset = 0,

like in the picture:

I save this config, regenerate HSSI Dual simplex IP, reassign pin locations for rx, so they occupy channels 0 - 2. All the rest assignments stay unchanged.

In that case the fitter is not able to succeed.

Then I've removed all pin assignments to allow the fitter to find the right place by itself. But it still is not able to fit.

At the other hand, the Quartus 24.2 was able to do this. But when I take pin assignments from q24 (which were successfulluy fit) and give them to q25, it is still not happy.

Has someone any ideas, how to fit my configuration?

Than you.

13 Replies

  • Aleh_TS's avatar
    Aleh_TS
    Icon for New Contributor rankNew Contributor

    Thank you, WIncent.

    Unfortunately, your project has the same problem. Fitter-Plan is not able to find a legal placement.

    I use q25.1.0 build 129, patch 0.36

    Which one did you use?

    BR

    Aleh

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor

      Hi AlehTS​ ,

      Is weird, because I can get it pass 100 %
      I am using "QUARTUS_VERSION "25.1.0 SP0.36 Pro Edition"



      Regards,
      Wincent

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor

        Hi Aleh_TS​ ,

        I guess, I sent you a wrong file, let me check back if I still got the file or not, else I will generate a brand new and sent to you again.
        At the meantime, an you please try to remove the top file then replace with the one I share you earlier and try to recompile again ?

        Regards,
        Wincent

  • Aleh_TS's avatar
    Aleh_TS
    Icon for New Contributor rankNew Contributor

    Hi Wincent.

    My .v code is correct. Analysis and Synthesis pass well. The problem is in fitter.

    Anyway, can you send me the whole your project (.qar), please.

    Thank you.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi Aleh_TS 

    I have attached the updated top.v file.
    1) sda and scl signal is not connected at top.v
    2) syspll_clk is mistakenly connected to syspll_lock signal.

    Please try to adding the  sda and scl signal in top.v and removing the connection between syspll_clk  and syspll_lock
    With the update i able to get the compilation passing. Can you please try it out ?
    Else I would suggest you to continue with v24.2 which is working well - it save your effort.

    Regards,

    Wincent_Altera