UserID4331231
Occasional Contributor
Occasional ContributorAddress range confusion for AVMM Host to multiple AVMM Agent.
Attached is the screen shot from Platform designer, this is example design from BAS+MCDMA and I am trying to add AVMM FIFO for my usecase.
I have a AVMM Host from BAR interpreter module which is connected to two AVMM agent ports on BAM Memory and BAS TGC module in original example design. For my usecase i want to connect AVMM FIFO as third AVMM agent. My FIFO "depth" is 16 and "data width" is set to 256
I was able to make connection in Platform designer as you can see in the 1st screen shot. While analyzing address range in second screen shot, I see FIFO AVMM agent port is assigned 32bytes of address range.
my questions are Assuming I am writing my own logic to drive this AVMM Host interface
- AVMM BAM Master has 512 bit write data bus Vs my FIFO width is 256 bit. the other AVMM agent interface has writedata of 512 bits. is this valid configuration? i mean there is writedata width mismatch across agents.
- To issue writes to FIFO, what address AVMM Master need to drive ? i see 32 byte address range 0x0 to 0x1F.
- can I use any offset between 0x0 to 0x1F and drive data on [255:0] writedata with proper byte enables? or does offset need to be 0x0.?
- AVMM agent port on FIFO is 256 bit wide, and AVMM master writedata is 512 bit wide; so I am thinking if use offset 0x0, drive 512 bits of data but byteenable as 32{1'b1}; it would work ; is that correct understanding?
- I am curious how AVMM Host handles Waitrequest from multiple AVMM agents?
- I mean Host interface only have one waitrequest input.
- and there is one wait request from each agent. if a waitrequest is asserted from an agent it only means that agent is busy, other agents are free and can serve AVMM Host requests.
- Is Quartus auto generating such bus management logic for each AVMM bus (one AVMM Host and One or more of AVMM agents)?
