Address range confusion for AVMM Host to multiple AVMM Agent.

1. Yes, it is valid for Avalon MM agents to have different data widths when connected to a single Avalon MM host in Platform Designer. The interconnect logic generated by Platform Designer automatically handles data width adaptation between the host and each agent.

https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1/width-adaptation-84420.html

2. can I use any offset between 0x0 to 0x1F and drive data on [255:0] writedata with proper byte enables? or does offset need to be 0x0.?

You can use any aligned offset within this range to issue writes. Check the Avalon MM Agent Addressing

https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/mm-agent-addressing.html

AVMM agent port on FIFO is 256 bit wide, and AVMM master writedata is 512 bit wide; so I am thinking if use offset 0x0, drive 512 bits of data but byteenable as 32{1'b1}; it would work ; is that correct understanding?

The width adapter will handle this conversion for you. The master can still issue 512-bit writes, and the adapter will split them into two 256-bit writes internally. So yes, your conceptual understanding is correct, but you don’t manually control the two 256-bit transactions; PD-generated logic does that. During host write transfers, the interconnect automatically asserts the byteenable signals to write data only to the specified agent byte lanes.

3. Yes, Platform Designer automatically inserts arbitration logic, which grants access in fairness-based, round-robin order. You do not need to implement this logic yourself. https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1/arbitration.html

For further details, checkout the Avalon® Memory-Mapped Interfaces 3.5 Transfers

https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/transfers.html

Regards,

Richard Tan