A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi @Sijith,

As per your modification, you want to use the counter to generate data and stream the data to DDR4 through FIFO. But when looking into your qsys file (in the attached screenshot) , I found that the Avalon FIFO is not connected to the DDR4. May I know why the Avalon FIFO is connected directly to DMA instead DDR4? The data from the FIFO should be first stored in the DDR4 right?

You may try to generate the Example Design from the External Memory Interfaces Intel Aria 10 IP to view the connections of the DDR4 and data generator.

To keep your EMIF IP configuration settings, open the .qsys of your current design in Platform Designer, click the EMIF IP, and click Generate Example Design in the Parameters tab.

Since you're able to run the example design without modification previously, this means that the DMA is working. Then, we need to check on the data transmitted from the data generator (counter) to ensure it is correctly stored in the DDR4. Can you please run the Signal Tap to check the DDR4 as well?

Thanks.

Best Regards,

VenTing_Intel