A code reviewer has suggested that my main 50MHz input clock from an external crystal oscillator should be input to a PLL within the FPGA to produce a cleaner internal 50MHz clock, i.e. glitches on the external clock will be ignored. Is this true?

Hi,

In the FPGA, the clock must be connected to the dedicated clock input pins [clk0p/n, clk1p/n..... ] to get the external clock to the clock network of FPGA. But usage of PLL is not necessary unless you want to have some kind of clock synthesis.

However, the input clock connected to dedicated pins can be used in the design without any PLL.

module test (
 
input wire clock,
input wire reset,
output reg toggle
);
 
always @ ( posedge clock) begin 
  if (reset) begin
    toggle <= 1'b0;
  end else begin
    toggle <= ~ toggle;
  end
end
 
endmodule

With Regards,

HPB

Hi Fergus Robertson

PLL provides synchronization between external clock and internal clocks. A slight change at external clock does not vary the PLL frequency.

When a PLL locks onto the input frequency, there is a limited variation of that signal at the output. This is good for jitter reduction and clock skew control of the design.

Thanks.

Eng Wei

Hi Fergus Robertson

Let me know if you have any further request on this topic before we go ahead to close the ticket.

Thanks.

Eng Wei