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FRobe6's avatar
FRobe6
Icon for New Contributor rankNew Contributor
5 years ago

A code reviewer has suggested that my main 50MHz input clock from an external crystal oscillator should be input to a PLL within the FPGA to produce a cleaner internal 50MHz clock, i.e. glitches on the external clock will be ignored. Is this true?

I have only ever used a PLL within an FPGA to multiply, or divide, the incoming clock frequency, or phase shift the incoming clock. I have never used a PLL if the design only has one clock frequency...
HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

Hi,

In the FPGA, the clock must be connected to the dedicated clock input pins [clk0p/n, clk1p/n..... ] to get the external clock to the clock network of FPGA. But usage of PLL is not necessary unless you want to have some kind of clock synthesis.

However, the input clock connected to dedicated pins can be used in the design without any PLL. 

module test (
 
input wire clock,
input wire reset,
output reg toggle
);
 
always @ ( posedge clock) begin 
  if (reset) begin
    toggle <= 1'b0;
  end else begin
    toggle <= ~ toggle;
  end
end
 
endmodule

With Regards,

HPB