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FRobe6's avatar
FRobe6
Icon for New Contributor rankNew Contributor
6 years ago

A code reviewer has suggested that my main 50MHz input clock from an external crystal oscillator should be input to a PLL within the FPGA to produce a cleaner internal 50MHz clock, i.e. glitches on the external clock will be ignored. Is this true?

I have only ever used a PLL within an FPGA to multiply, or divide, the incoming clock frequency, or phase shift the incoming clock. I have never used a PLL if the design only has one clock frequency...
EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Fergus Robertson

Let me know if you have any further request on this topic before we go ahead to close the ticket.

Thanks.

Eng Wei

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi Fergus Robertson

    We do not receive any response from you to the previous feedback that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

    Eng Wei.