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FRobe6's avatar
FRobe6
Icon for New Contributor rankNew Contributor
5 years ago

A code reviewer has suggested that my main 50MHz input clock from an external crystal oscillator should be input to a PLL within the FPGA to produce a cleaner internal 50MHz clock, i.e. glitches on the external clock will be ignored. Is this true?

I have only ever used a PLL within an FPGA to multiply, or divide, the incoming clock frequency, or phase shift the incoming clock. I have never used a PLL if the design only has one clock frequency...
EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Fergus Robertson

PLL provides synchronization between external clock and internal clocks. A slight change at external clock does not vary the PLL frequency.

When a PLL locks onto the input frequency, there is a limited variation of that signal at the output. This is good for jitter reduction and clock skew control of the design.

Thanks.

Eng Wei