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Altera_Forum's avatar
Altera_Forum
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11 years ago

10GBASE-R PHY Management Interface

Hi,

I am trying to connect this management interface (not available in Qsys yet) to Qsys interconnect:

http://www.alteraforum.com/forum/attachment.php?attachmentid=10197&stc=1

http://www.alteraforum.com/forum/attachment.php?attachmentid=10217&stc=1

I used an Avalon MM Slave Translator (address 0000_0000 to 0000_07FF) in Qsys:

http://www.alteraforum.com/forum/attachment.php?attachmentid=10198&stc=1

but when I try to write to another module in 0x0000_1000 to 0x0000_10FF range, the Qsys router calls this module instead and not the other one at base address 0x0000_1000. How can I fix this problem in Qsys?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I am really stuck. Can someone help me to connect this management interface to the Avalon interconnect through Qsys?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Seems like this is a bug in Qsys... I set the anti-slave address width to 9 bits but Qsys ignores it and sets to 32 bits. Why??? 

    altera_merlin_slave_translator# (        .AV_ADDRESS_W                   (32),
        .AV_DATA_W                      (32),
        .UAV_DATA_W                     (32),
        .AV_BURSTCOUNT_W                (3),
        .AV_BYTEENABLE_W                (4),
        .UAV_BYTEENABLE_W               (4),
        .UAV_ADDRESS_W                  (32),
        .UAV_BURSTCOUNT_W               (3),
        .AV_READLATENCY                 (0),
        .USE_READDATAVALID              (1),
        .USE_WAITREQUEST                (1),
        .USE_UAV_CLKEN                  (0),
        .USE_READRESPONSE               (0),
        .USE_WRITERESPONSE              (0),
        .AV_SYMBOLS_PER_WORD            (4),
        .AV_ADDRESS_SYMBOLS             (1),
        .AV_BURSTCOUNT_SYMBOLS          (1),
        .AV_CONSTANT_BURST_BEHAVIOR     (0),
        .UAV_CONSTANT_BURST_BEHAVIOR    (0),
        .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
        .CHIPSELECT_THROUGH_READLATENCY (0),
        .AV_READ_WAIT_CYCLES            (0),
        .AV_WRITE_WAIT_CYCLES           (0),
        .AV_SETUP_WAIT_CYCLES           (0),
        .AV_DATA_HOLD_CYCLES            (0)
    ) phy_mgmt_slave_avalon_universal_slave_0_translator (
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I figured it out:

    http://www.alterawiki.com/wiki/new_qsys_issues

    Merlin Address Routers for Custom peripherals

    Issue: When generating the system, Merlin address routers are generated ignoring the ExplicitAddressSpan Avalon property. This causes channels to be greater than the complete address space in some cases; for instance, for a system that uses 29 bits of address space (512 MBs), with explicitly using only 16 MBs, Merlin address routers are generated with full 29 bits of address space per channel. Since the complete address space defaults to the size of the address space of the biggest addressable peripheral, this later causes errors in compilation (Verilog errors containing "...part-select direction is opposite from prefix index direction...") and also address space is overlapped with other peripherals with smaller address spaces.

    Workaround: Manually edit nios_addr_router.sv files (there will be more of them; they are located under \{nios_name}\synthesis\submodules\ directory in your project directory) and manually set the values of the PADx variables to the desired address space size (ExplicitAddressSpanValue = 2^PADxValue). Do not change the value of the complete address space (RG variable), as this might introduce more problems.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I don't know anything about the core but if it's not available in Qsys then I would create a gasket component that simply exposes all those wires/buses and connects them to a conduit that you expose to the top level. The HDL will just be wires and you can connect them in the top level up to that 10G core. In Qsys is a program called component editor which you feed HDL into to build a component that you can instantiate in Qsys. When you write the HDL just make sure you match all the signals and their widths so that you can wire the slave 1:1 to the conduit wires.

    That slave translator is primarily used by Qsys at generation time to adapt Avalon-MM interfaces to something called "universal Avalon". It's not intended to expose slave interfaces outside of Qsys systems.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks BadOmen. I replied but my reply didn't go through. I finally figured it out. It's a known bug: http://www.alterawiki.com/wiki/new_qsys_issues

    Merlin Address Routers for Custom peripherals

    Issue: When generating the system, Merlin address routers are generated ignoring the ExplicitAddressSpan Avalon property. This causes channels to be greater than the complete address space in some cases; for instance, for a system that uses 29 bits of address space (512 MBs), with explicitly using only 16 MBs, Merlin address routers are generated with full 29 bits of address space per channel. Since the complete address space defaults to the size of the address space of the biggest addressable peripheral, this later causes errors in compilation (Verilog errors containing "...part-select direction is opposite from prefix index direction...") and also address space is overlapped with other peripherals with smaller address spaces.

    Workaround: Manually edit nios_addr_router.sv files (there will be more of them; they are located under \{nios_name}\synthesis\submodules\ directory in your project directory) and manually set the values of the PADx variables to the desired address space size (ExplicitAddressSpanValue = 2^PADxValue). Do not change the value of the complete address space (RG variable), as this might introduce more problems.

    I solved it by modifying the routing file as explained above.

    P.S: Nice avatar! Go HABS Go!
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks BadOmen for the reply. It's a known bug on Altera Wiki:

    --- Quote Start ---

    Merlin Address Routers for Custom peripherals

    Issue: When generating the system, Merlin address routers are generated ignoring the ExplicitAddressSpan Avalon property. This causes channels to be greater than the complete address space in some cases; for instance, for a system that uses 29 bits of address space (512 MBs), with explicitly using only 16 MBs, Merlin address routers are generated with full 29 bits of address space per channel. Since the complete address space defaults to the size of the address space of the biggest addressable peripheral, this later causes errors in compilation (Verilog errors containing "...part-select direction is opposite from prefix index direction...") and also address space is overlapped with other peripherals with smaller address spaces.

    Workaround: Manually edit nios_addr_router.sv files (there will be more of them; they are located under \{nios_name}\synthesis\submodules\ directory in your project directory) and manually set the values of the PADx variables to the desired address space size (ExplicitAddressSpanValue = 2^PADxValue). Do not change the value of the complete address space (RG variable), as this might introduce more problems.

    --- Quote End ---

    P.S: Go HABS Go! ;)