10GBASE-R PHY Management Interface

I don't know anything about the core but if it's not available in Qsys then I would create a gasket component that simply exposes all those wires/buses and connects them to a conduit that you expose to the top level. The HDL will just be wires and you can connect them in the top level up to that 10G core. In Qsys is a program called component editor which you feed HDL into to build a component that you can instantiate in Qsys. When you write the HDL just make sure you match all the signals and their widths so that you can wire the slave 1:1 to the conduit wires.

That slave translator is primarily used by Qsys at generation time to adapt Avalon-MM interfaces to something called "universal Avalon". It's not intended to expose slave interfaces outside of Qsys systems.