Forum Discussion
Contributor100G Ethernet MAC : Transceiver configuration
Hi,
I was looking at 100G low latency MAC Hard IP in stratix 10 FPGA. Here, I observed that 100G is achieved by 4 lanes of transceiver channels each running at 25Gbps. My understanding is Internally in the MAC, the payload will be distributed to 4 transmitting channels and receiver receives the contents in 4 different RX and combines to form the actual payload data.
But, the design doesn't employ any channel bonding. I am curious how the skew is taken care in the PMA without employing channel bonding (PMA-only) as all the 4 channels carry part of the same payload.
What is the logic behind this (not having channel bonding for x4 channels to support 100G)?
With regards,
HPB
13 Replies
Deshi_IntelRegular Contributor
Hi HPB, There is deskew buffer design in RX PCS path to manage the skew induced within the 4 channels. Thanks. Regards, dlim- HBhat2
Hi @DeshiL_Intel ,
In my view, Deskew buffer will take care the PCS skew. How about PMA? Whether PMAs for 4 channels will not contribute to the channel skew?
With Regards,
HPB
- Deshi_IntelHi HPB, For the RX path, the data traffic needs to pass through PMA first before reaching PCS. All the channel to channel skew impact will be carry forward to PCS path also which will be taken care by deskew buffer logic. Thanks. Regards, dlim
- HBhat2
Hi @DeshiL_Intel ,
Understood.
Basically de-skewing is done similar to the FSM mentioned in the XCVR user guide, page 218
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf
On the TX side, I think soft bonding is also performed as in page 216 of above link.
By the way, Can I get a rough idea of how much skew could be added by the PMA blocks for at least 2 channels in a XCVR bank?
Also, for 100G spec, I believe that the PMA skew requirement is 13ns max. on each direction.
With Regards,
HPB
- Deshi_IntelHi HPB, Sorry about that. I found XCVR channel to channel skew spec of 61ps from Stratix 10 datasheet doc in below link https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf You can refer to datasheet table 43 and table 54. Thanks. Regards, dlim
- HBhat2
Hi,
I think, above data is for x6 bonded configuration. As I am not using Master CGB, above data is not useful. I think we need to refer to transceiver user guide, page 300 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf
3.9.4. Skew Calculations.
With Regards,
HPB
- Deshi_IntelHi HPB, I think you can checkout the FPGA package length report between 2 XCVR channel in below link. goto tools, models, and Libraries -> Net length reports https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/board-design-guidelines.html#Tools--Models--and-Libraries Thanks. Regards, dlim
- HBhat2
Hi,
I checked it. Unfortunately, the report doesn't cover transceiver IOs.
With Regards,
HPB
- Deshi_IntelHi HPB, The datasheet shown both spec for x6 and x24 but you are right, the spec is meant for CGB bonding configuration and you are not using it. Yes, as alternative, you can also refer to user guide chapter 3.9.4 Thanks. Regards, dlim
- HBhat2
Hi @DeshiL_Intel ,
Is there any special skew calculation/estimation method for adjacent channels in a bank other than 3.9.4. Skew Calculations. In my view, the skew must be minimum between adjacent channels and increases with channel neighborhood. Correct me if my understanding is wrong.
With regards,
HPB
- Deshi_Intel
Hi HPB,
Sorry, we don't have other calculation method.
Regards,
dlim
- Deshi_Intel
Hi HPB,
Have you generated 100G Ethernet example design and checkout the NativePHY setting in it ?
Thanks.
Regards,
dlim
