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HBhat2's avatar
HBhat2
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6 years ago

100G Ethernet MAC : Transceiver configuration

Hi, I was looking at 100G low latency MAC Hard IP in stratix 10 FPGA. Here, I observed that 100G is achieved by 4 lanes of transceiver channels each running at 25Gbps. My understanding is Internall...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi HPB, For the RX path, the data traffic needs to pass through PMA first before reaching PCS. All the channel to channel skew impact will be carry forward to PCS path also which will be taken care by deskew buffer logic. Thanks. Regards, dlim
HBhat2's avatar
HBhat2
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6 years ago

Hi @DeshiL_Intel​ ,

Understood.

Basically de-skewing is done similar to the FSM mentioned in the XCVR user guide, page 218

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf

On the TX side, I think soft bonding is also performed as in page 216 of above link.

By the way, Can I get a rough idea of how much skew could be added by the PMA blocks for at least 2 channels in a XCVR bank?

Also, for 100G spec, I believe that the PMA skew requirement is 13ns max. on each direction.

With Regards,

HPB