HBhat2Contributor7 years ago100G Ethernet MAC : Transceiver configuration Hi, I was looking at 100G low latency MAC Hard IP in stratix 10 FPGA. Here, I observed that 100G is achieved by 4 lanes of transceiver channels each running at 25Gbps. My understanding is Internall...Show More
Deshi_IntelRegular Contributor7 years agoHi HPB, There is deskew buffer design in RX PCS path to manage the skew induced within the 4 channels. Thanks. Regards, dlim
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