Forum Discussion
HBhat2
Contributor
Contributor100G Ethernet MAC : Transceiver configuration
Hi, I was looking at 100G low latency MAC Hard IP in stratix 10 FPGA. Here, I observed that 100G is achieved by 4 lanes of transceiver channels each running at 25Gbps. My understanding is Internall...
Deshi_Intel
Regular Contributor
Regular ContributorHi HPB,
There is deskew buffer design in RX PCS path to manage the skew induced within the 4 channels.
Thanks.
Regards,
dlim
