Forum Discussion
HBhat2
Contributor
Contributor100G Ethernet MAC : Transceiver configuration
Hi, I was looking at 100G low latency MAC Hard IP in stratix 10 FPGA. Here, I observed that 100G is achieved by 4 lanes of transceiver channels each running at 25Gbps. My understanding is Internall...
Deshi_Intel
Regular Contributor
Regular ContributorHi HPB,
I think you can checkout the FPGA package length report between 2 XCVR channel in below link.
goto tools, models, and Libraries -> Net length reports
https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/board-design-guidelines.html#Tools--Models--and-Libraries
Thanks.
Regards,
dlim
HBhat2Contributor
ContributorHi,
I checked it. Unfortunately, the report doesn't cover transceiver IOs.
With Regards,
HPB
