Forum Discussion

Contributor

6 years ago

100G Ethernet MAC : Transceiver configuration

Hi, I was looking at 100G low latency MAC Hard IP in stratix 10 FPGA. Here, I observed that 100G is achieved by 4 lanes of transceiver channels each running at 25Gbps. My understanding is Internall...

Deshi_Intel

Regular Contributor

6 years ago

Hi HPB, Sorry about that. I found XCVR channel to channel skew spec of 61ps from Stratix 10 datasheet doc in below link https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf You can refer to datasheet table 43 and table 54. Thanks. Regards, dlim

HBhat2
Contributor
6 years ago
Hi,
I think, above data is for x6 bonded configuration. As I am not using Master CGB, above data is not useful. I think we need to refer to transceiver user guide, page 300 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf
3.9.4. Skew Calculations.
With Regards,
HPB

Forum Discussion

100G Ethernet MAC : Transceiver configuration

Recent Discussions

F-Tile xcvr placement on DK-DEV-AGF023FA

Cyclone-V SCFIFO with M10K/MLAB memory - adding ECC

Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted

Connecting Intel Agilex FPGA to DE1-SoC via Hub

Agilex 7 I Series Development Kit: External hardware access error when programming