Why 10AS016C4U19E3SG could use the x16 DDR4 component upper byte lane[DQ8~DQ15] for ECC?

Hi team,

there are three x16 DDR4 components 【MT40A512M16LY-075:E】 in my board, The upper 8 bits of the lastcomponents are used for ECC. but I learn about a rule from Micron application note：When using a x16 component for ECC, the lower byte lane (DQ[7:0]) must be used for the ECC bits.DDR4 memory is capable of per-DRAM addressability (PDA), and this function is used during the DDR4 device initialization sequence for VREFDQ calibration. PDA is enabled by DQ0, so the lower byte lane must be used and connected to the controller.

Does Arria10 SOC FPGA has this limitation? thank you ！