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Kevin52
New Contributor
New ContributorWhy 10AS016C4U19E3SG could use the x16 DDR4 component upper byte lane[DQ8~DQ15] for ECC?
Hi team, there are three x16 DDR4 components 【MT40A512M16LY-075:E】 in my board, The upper 8 bits of the lastcomponents are used for ECC. but I learn about a rule from Micron applicatio...
yoichiK_altera
Contributor
ContributorHi
The restrictions on I/O bank usage result from the Arria® 10 HPS having hard-wired connections to the EMIF circuits in the I/O banks closest to the HPS. For any given EMIF configuration, the pin-out of the EMIF-to-HPS interface is fixed. Please refer to the following link for the detail.
