Why 10AS016C4U19E3SG could use the x16 DDR4 component upper byte lane[DQ8~DQ15] for ECC?

The restrictions on I/O bank usage result from the Arria® 10 HPS having hard-wired connections to the EMIF circuits in the I/O banks closest to the HPS. For any given EMIF configuration, the pin-out of the EMIF-to-HPS interface is fixed. Please refer to the following link for the detail.