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New Contributor

3 months ago

Why 10AS016C4U19E3SG could use the x16 DDR4 component upper byte lane[DQ8~DQ15] for ECC?

Hi team, there are three x16 DDR4 components 【MT40A512M16LY-075:E】 in my board, The upper 8 bits of the lastcomponents are used for ECC. but I learn about a rule from Micron applicatio...

yoichiK_intel

Contributor

3 months ago

sorry ,miss understood your question. Please connect Arria10 ECC lane to lower byte lane DQ[7:0] of DDR4 component as micron technical note says.

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Why 10AS016C4U19E3SG could use the x16 DDR4 component upper byte lane[DQ8~DQ15] for ECC?

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