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Altera_Forum's avatar
Altera_Forum
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15 years ago

weird dma transfer behavoir

have set up a simple hardware system where the nios writes data to a on-chip fifo, and a dma transfer it back to sdram. datawidth is 32 all the way. i also use rxchan_ioctl to set dma to 32 bit

first i do 32 writes, seeminly okay - but when i tell the dma to get it i must set the length parameter to 128 to empty the fifo. why dont i fetch number of words equal to length?

also the first five words are not fetched correctly, why is that?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The length register uses a byte format. So to move 32 words of width 32-bits that's 128 bytes you are moving.

    If you are seeing data corruption make sure you are bypassing the cache or flushing it before kicking off the DMA.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    i now do a alt_dcache_flush_all before i "rxchan_prepare", but the first five words are still not transfered. prepare simply dont put anything there.

    a new issue also came up. fifo_init now returns -1 wich means event clear error. what could cause this? an address issue?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Off the top of my head I'm not sure (I typically access the DMA registers directly.... and I haven't used that DMA in years). I would take a look at this document since the HAL portions of the DMA are documented in there: http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf Also I would use the macros in the DMA driver to read back the status register, you may see a bit in there that might explain what happened.