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Altera_Forum
Honored Contributor
Honored Contributorweird dma transfer behavoir
have set up a simple hardware system where the nios writes data to a on-chip fifo, and a dma transfer it back to sdram. datawidth is 32 all the way. i also use rxchan_ioctl to set dma to 32 bit ...
Altera_ForumHonored Contributor
Honored Contributori now do a alt_dcache_flush_all before i "rxchan_prepare", but the first five words are still not transfered. prepare simply dont put anything there.
a new issue also came up. fifo_init now returns -1 wich means event clear error. what could cause this? an address issue?
