Probably dumb question but does setting a virtual pin value to ON imply that it will be at logic 1 state in the compiled design during user mode? For instance vpin1=1'b1 and vpin2=1'b0 resulting from the below assignments:set_instance_assignment -name VIRTUAL_PIN ON -to vpin1 set_instance_assignment -name VIRTUAL_PIN OFF -to vpin2If not how do we set a run-time state for virtual pins?

Hi,virtual pin assignment removes a top entity port pint from the actual port list.You can assign an initial value to the pin to achieve what you want.

No. As stated, setting a top-level signal with the VIRTUAL_PIN assignment ON means that that signal will be routed to a logic "stub" in the FPGA fabric instead of to an I/O pin. This is usually used if you don't yet know what specific I/O pin you want to use, but you don't want the compiler to optimize away the signal because it's not connected to anything. There's even a quick video on this! https://www.youtube.com/watch?v=QET0lC-jdAQ

Hi FvM -- ok that makes sense and more specifically implies SV 2009 or later (for default port values) -- I will try

Hi sstrell -- thanks I watched that video before posting but did not pick up what the port logic value used by the compiled design when running would be -- my questions arising are:does default port value method suggested by FvM put a fixed know value for the virtual pin port signal?what happens if you set the virtual pin value to OFF instead of ON?

1) Value will be low at configuration on most devices as it is with all other signals (presuming you are talking about an input, not an output, here). On Stratix 10, you can initialize signals to high on configuration. 2) Not much. You're basically saying the signal must be attached to a pin location, and if it's not, it could get optimized away.

Virtual Pin Assignments -- does Value=Off/On imply logic 0/1 for pin?

13 Replies

FvM
Super Contributor
2 years ago
Hi,
virtual pin assignment removes a top entity port pint from the actual port list.
You can assign an initial value to the pin to achieve what you want.
- sstrell
  Super Contributor
  2 years ago
  No. As stated, setting a top-level signal with the VIRTUAL_PIN assignment ON means that that signal will be routed to a logic "stub" in the FPGA fabric instead of to an I/O pin. This is usually used if you don't yet know what specific I/O pin you want to use, but you don't want the compiler to optimize away the signal because it's not connected to anything. There's even a quick video on this! https://www.youtube.com/watch?v=QET0lC-jdAQ
  - Steve-Mowbray-ENL
    Occasional Contributor
    2 years ago
    Hi sstrell -- thanks I watched that video before posting but did not pick up what the port logic value used by the compiled design when running would be -- my questions arising are:
    does default port value method suggested by FvM put a fixed know value for the virtual pin port signal?
    what happens if you set the virtual pin value to OFF instead of ON?
- Steve-Mowbray-ENL
  Occasional Contributor
  2 years ago
  Hi FvM -- ok that makes sense and more specifically implies SV 2009 or later (for default port values) -- I will try
TingJiangT_Intel
Contributor
2 years ago
Hi there, may I know why you need to know the initial value of the virtual pins. Do you need to do simulation?
Virtual pin usually used to do some optimization in timing and resources usage, so normally it won't be the final version of your design.
- Steve-Mowbray-ENL
  Occasional Contributor
  2 years ago
  top level file is reused between multiple projects on different target hardware -- we can reuse the top level file with virtual pins on lesser hardware so long as the state of the virtual pin is fixed known in the lesser hardware project -- improved hardware will have the pin as physical and the state will come from external source
TingJiangT_Intel
Contributor
2 years ago
I found the following information which may provide reference:
https://www.intel.com/content/www/us/en/support/programmable/articles/000073765.html

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Virtual Pin Assignments -- does Value=Off/On imply logic 0/1 for pin?

13 Replies

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