Occasional Contributor
Super ContributorHi,
virtual pin assignment removes a top entity port pint from the actual port list.
You can assign an initial value to the pin to achieve what you want.
Super ContributorNo. As stated, setting a top-level signal with the VIRTUAL_PIN assignment ON means that that signal will be routed to a logic "stub" in the FPGA fabric instead of to an I/O pin. This is usually used if you don't yet know what specific I/O pin you want to use, but you don't want the compiler to optimize away the signal because it's not connected to anything. There's even a quick video on this! https://www.youtube.com/watch?v=QET0lC-jdAQ
Occasional ContributorHi sstrell -- thanks I watched that video before posting but did not pick up what the port logic value used by the compiled design when running would be -- my questions arising are:
Super Contributor1) Value will be low at configuration on most devices as it is with all other signals (presuming you are talking about an input, not an output, here). On Stratix 10, you can initialize signals to high on configuration.
2) Not much. You're basically saying the signal must be attached to a pin location, and if it's not, it could get optimized away.
Occasional ContributorHi FvM -- ok that makes sense and more specifically implies SV 2009 or later (for default port values) -- I will try
