VHDL waveform simulation problems

The basic problem is that all signal assignments in the sequential code take effect after the end of the process. This also applies to iteration loops. In other words, the for loop has no effect at all.

Variable are in contrast updated immediately. A simple implementation can look like this, where count has to be defined as a variable inside the process. I suggest to review the topic in a VHDL text book or tutorial and won't give lengthy explanations on it.

count := "00";
for i in 7 downto 0 loop
  if (A(i) <= '1') then
    count := count + 1;
  end if;
end loop;

To represent the full range of 0 to 8 '1' bits, a 4-Bit counter would be required.

Thanks for replying

About the counter, I know it will always receive 8bits with no more than 3 '1' bit.

I admit I still have some issues to completely understand the use of signals.

I tried to fix it doing as you adviced

count is now a variable, I didn't know if I could assing a variable to an output

so I created another signal, "conta", and assigned the variable count to it inside the process, and so assigned "conta" to the output "contador" outside the process

Now the "contador" isn't adding for every clock pulse anymore, as a matter of fact, it isn't adding even when A(i) <= '1'.

I guess there may be a problem the way I attached the signals and variable inside/outside the process.

If my question is too basic, I would appreciate a link where I could understand it thoroughly. I got to send a project next friday.

Right now the code is like:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity contador_acertos is

port (clock, reset, enable : in std_logic;

acertos : in std_logic_vector(7 downto 0);

contador : out std_logic_vector(1 downto 0)

);

end contador_acertos;

architecture behavior_contagem of contador_acertos is

signal A : std_logic_vector(7 downto 0);

signal conta : std_logic_vector(1 downto 0);

begin

A <= acertos;

process (clock, acertos, enable, reset)

variable count : std_logic_vector(1 downto 0);

begin

if (reset = '1') then

count := "00";

elsif (clock'event and clock = '1') then

if (enable <= '1') then

count := "00";

oito : for i in 7 downto 0 loop

if (A(i) <= '1') then

count := count + 1;

end if;

end loop oito;

end if;

end if;

conta <= count;

end process;

contador <= conta;

end behavior_contagem;

Sorry for changing things too fast, but it took so long for someone to repost so I created it differently, but still not working...

it looks like my problem is with "cont" and "C". The code compile and looks fine, but the cont doesnt add when I simulate through vector waveform file with saida_reg_esquadra(7)='1' and

saida_reg_disparo(7)= '1'

in this code, when both "saidas" are 1, the cont is added by 1 only once

is it not working because cont is assigned to C within the process?

or because I should initiate signal S with 00000000?

have no idea, im struggling with this since today's morning

Now my new code is

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity comparador is

port (

clock : in std_logic;

reset : in std_logic;

saida_reg_esquadra : in std_logic_vector(7 downto 0);

saida_reg_disparo : in std_logic_vector(7 downto 0);

C : out std_logic_vector(1 downto 0)

);

end comparador;

architecture behavior of comparador is

signal S: std_logic_vector(7 downto 0);

signal cont: std_logic_vector(1 downto 0);

begin

process(clock, saida_reg_esquadra, saida_reg_disparo, reset)

begin

if (reset = '1') then

cont <="00";

elsif (clock'event and clock='1') then

if (saida_reg_esquadra(0) = '1' and saida_reg_disparo(0) ='1' and S(0) = '0') then

cont <= cont +1;

S(0) <='1';

elsif (saida_reg_esquadra(1) = '1' and saida_reg_disparo(1) ='1' and S(1) = '0') then

cont <= cont +1;

S(1) <='1';

elsif (saida_reg_esquadra(2) = '1' and saida_reg_disparo(2) ='1' and S(2) = '0') then

cont <= cont +1;

S(2) <='1';

elsif (saida_reg_esquadra(3) = '1' and saida_reg_disparo(3) ='1' and S(3) = '0') then

cont <= cont +1;

S(3) <='1';

elsif (saida_reg_esquadra(4) = '1' and saida_reg_disparo(4) ='1' and S(4) = '0') then

cont <= cont +1;

S(4) <='1';

elsif (saida_reg_esquadra(5) = '1' and saida_reg_disparo(5) ='1' and S(5) = '0') then

cont <= cont +1;

S(5) <='1';

elsif (saida_reg_esquadra(6) = '1' and saida_reg_disparo(6) ='1' and S(6) = '0') then

cont <= cont +1;

S(6) <='1';

elsif (saida_reg_esquadra(7) = '1' and saida_reg_disparo(7) ='1' and S(7) = '0') then

cont <= cont +1;

S(7) <='1';

end if;

end if;

C <= cont;

end process;

end behavior;

I just nailed it!!!!

I'll post it here, maybe someone will need it later.

The problem as I suspected was that S wasn't declared.

So to fix it, you have to write

signal S: std_logic_vector(7 downto 0):= (others => '0');

Yea, that was the problem...

...sigh "makes gun shape with hand, points to head, bang"

You have implemented a kind of state machine to perform the intended action sequentially, one bit per clock cycle.

That's the other solution for the present problem if the involved logic is too complex to determine the result in a single clock cycle. In the present case, a parallel solution as sketched in my previous post should perfectly work.

Technically, there are several points that possibly need to be changed with your code to use it in a real word application, but you'll surely find out when using it.