VHDL waveform simulation problems

You have implemented a kind of state machine to perform the intended action sequentially, one bit per clock cycle.

That's the other solution for the present problem if the involved logic is too complex to determine the result in a single clock cycle. In the present case, a parallel solution as sketched in my previous post should perfectly work.

Technically, there are several points that possibly need to be changed with your code to use it in a real word application, but you'll surely find out when using it.