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Altera_Forum's avatar
Altera_Forum
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14 years ago

VHDL waveform simulation problems

Hello everyone, this is my first post here. Thanks in advance for reading my problem. Well, I have to create a vhdl code for a 2bit counter, which receives 8bits, and adds 1 to the counter fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I just nailed it!!!!

I'll post it here, maybe someone will need it later.

The problem as I suspected was that S wasn't declared.

So to fix it, you have to write

signal S: std_logic_vector(7 downto 0):= (others => '0');

Yea, that was the problem...

...sigh "makes gun shape with hand, points to head, bang"