VHDL waveform simulation problems

The basic problem is that all signal assignments in the sequential code take effect after the end of the process. This also applies to iteration loops. In other words, the for loop has no effect at all.

Variable are in contrast updated immediately. A simple implementation can look like this, where count has to be defined as a variable inside the process. I suggest to review the topic in a VHDL text book or tutorial and won't give lengthy explanations on it.

count := "00";
for i in 7 downto 0 loop
  if (A(i) <= '1') then
    count := count + 1;
  end if;
end loop;

To represent the full range of 0 to 8 '1' bits, a 4-Bit counter would be required.