VHDL waveform simulation problems

Sorry for changing things too fast, but it took so long for someone to repost so I created it differently, but still not working...

it looks like my problem is with "cont" and "C". The code compile and looks fine, but the cont doesnt add when I simulate through vector waveform file with saida_reg_esquadra(7)='1' and

saida_reg_disparo(7)= '1'

in this code, when both "saidas" are 1, the cont is added by 1 only once

is it not working because cont is assigned to C within the process?

or because I should initiate signal S with 00000000?

have no idea, im struggling with this since today's morning

Now my new code is

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity comparador is

port (

clock : in std_logic;

reset : in std_logic;

saida_reg_esquadra : in std_logic_vector(7 downto 0);

saida_reg_disparo : in std_logic_vector(7 downto 0);

C : out std_logic_vector(1 downto 0)

);

end comparador;

architecture behavior of comparador is

signal S: std_logic_vector(7 downto 0);

signal cont: std_logic_vector(1 downto 0);

begin

process(clock, saida_reg_esquadra, saida_reg_disparo, reset)

begin

if (reset = '1') then

cont <="00";

elsif (clock'event and clock='1') then

if (saida_reg_esquadra(0) = '1' and saida_reg_disparo(0) ='1' and S(0) = '0') then

cont <= cont +1;

S(0) <='1';

elsif (saida_reg_esquadra(1) = '1' and saida_reg_disparo(1) ='1' and S(1) = '0') then

cont <= cont +1;

S(1) <='1';

elsif (saida_reg_esquadra(2) = '1' and saida_reg_disparo(2) ='1' and S(2) = '0') then

cont <= cont +1;

S(2) <='1';

elsif (saida_reg_esquadra(3) = '1' and saida_reg_disparo(3) ='1' and S(3) = '0') then

cont <= cont +1;

S(3) <='1';

elsif (saida_reg_esquadra(4) = '1' and saida_reg_disparo(4) ='1' and S(4) = '0') then

cont <= cont +1;

S(4) <='1';

elsif (saida_reg_esquadra(5) = '1' and saida_reg_disparo(5) ='1' and S(5) = '0') then

cont <= cont +1;

S(5) <='1';

elsif (saida_reg_esquadra(6) = '1' and saida_reg_disparo(6) ='1' and S(6) = '0') then

cont <= cont +1;

S(6) <='1';

elsif (saida_reg_esquadra(7) = '1' and saida_reg_disparo(7) ='1' and S(7) = '0') then

cont <= cont +1;

S(7) <='1';

end if;

end if;

C <= cont;

end process;

end behavior;