VHDL waveform simulation problems

Thanks for replying

About the counter, I know it will always receive 8bits with no more than 3 '1' bit.

I admit I still have some issues to completely understand the use of signals.

I tried to fix it doing as you adviced

count is now a variable, I didn't know if I could assing a variable to an output

so I created another signal, "conta", and assigned the variable count to it inside the process, and so assigned "conta" to the output "contador" outside the process

Now the "contador" isn't adding for every clock pulse anymore, as a matter of fact, it isn't adding even when A(i) <= '1'.

I guess there may be a problem the way I attached the signals and variable inside/outside the process.

If my question is too basic, I would appreciate a link where I could understand it thoroughly. I got to send a project next friday.

Right now the code is like:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity contador_acertos is

port (clock, reset, enable : in std_logic;

acertos : in std_logic_vector(7 downto 0);

contador : out std_logic_vector(1 downto 0)

);

end contador_acertos;

architecture behavior_contagem of contador_acertos is

signal A : std_logic_vector(7 downto 0);

signal conta : std_logic_vector(1 downto 0);

begin

A <= acertos;

process (clock, acertos, enable, reset)

variable count : std_logic_vector(1 downto 0);

begin

if (reset = '1') then

count := "00";

elsif (clock'event and clock = '1') then

if (enable <= '1') then

count := "00";

oito : for i in 7 downto 0 loop

if (A(i) <= '1') then

count := count + 1;

end if;

end loop oito;

end if;

end if;

conta <= count;

end process;

contador <= conta;

end behavior_contagem;