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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL Protected type help

Hi everyone,..

I'm new in VHDL and FPGA, sorry for my lame question.

Here I have a project, and I thing I will need to use shared variable, here is the code I made :

--- Quote Start ---

library ieee;

use ieee.std_logic_1164.all;

-- Shared Function

package shared_function is

type sh_data is protected

procedure reset;

procedure set(signal new_data : std_logic);

impure function get_data return std_logic;

end protected sh_data;

end shared_function;

package body shared_function is

type sh_data is protected body

variable data : std_logic;

procedure reset is

begin

data := '0';

end reset;

procedure set(signal new_data : std_logic) is

begin

data := new_data;

end procedure;

impure function get_data return std_logic is

begin

return data;

end function;

end protected body sh_data;

end shared_function;

--- Quote End ---

When I perform "Start Compilation" or "Analyze Current File" in Quartus II Processing menu, I got these error messages :

--- Quote Start ---

Error (10500): VHDL syntax error at shared_function.vhd(6) near text "protected"; expecting "(", or "access", or "array", or "file", or "range", or "record"

Error (10500): VHDL syntax error at shared_function.vhd(10) near text "protected"; expecting ";", or an identifier ("protected" is a reserved keyword), or "package"

Error (10523): Ignored construct shared_function at shared_function.vhd(5) due to previous errors

Error (10500): VHDL syntax error at shared_function.vhd(14) near text "protected"; expecting "(", or "access", or "array", or "file", or "range", or "record"

Error (10500): VHDL syntax error at shared_function.vhd(31) near text "protected"; expecting ";", or an identifier ("protected" is a reserved keyword), or "package"

Error: Quartus II Analyze Current File was unsuccessful. 5 errors, 0 warnings

Error: Peak virtual memory: 185 megabytes

Error: Processing ended: Mon Mar 22 20:38:45 2010

Error: Elapsed time: 00:00:07

Error: Total CPU time (on all processors): 00:00:01

--- Quote End ---

I use Altera Quartus II version 9.1 SP1 Subscription Edition and I have changed the VHDL input to VHDL 2008.

Really, I don't understand at all, someone help me, please tell me what makes it error,

Any kind of help will be greatly appreciated...

Thanks :)

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    VHDL protected type isn't specified by VHDL 1993, the Quartus supported VHDL version.

    Seriously, I don't see, that it has any relevance for synthesizable logic (neither shared variables have in my opinion), but you may want to explain your intention in this regard.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks Mr. FvM

    But I think it's specified in VHDL 2008, and I have change the VHDL input to VHDL 2008 in "Setting -> Analysis & Synthesis -> VHDL input". Is Altera Quartus II really support VHDL 2008?

    I need those function to design somekind of clock detector system, here the explanation :

    --- Quote Start ---

    The system should be able to detect if there is clock feeded to this system and it should be able to detect if that series of clock ended. So I think this system should be able to detect both of rising and falling edge of clock input, and I manage to deal with it using 2 processes, because of I used 2 processes then I need a variable that can be accessed from both processes, and I found shared variable in VHDL 2008

    This is the timing :

    1. ___| | | | | | | | | | | | | | |____ -> 6 MHz clock input

    2. |||||||||||||||||||||||||||||||| -> 24 Mhz FPGA global clock input

    3. _________________________|___ -> Hi signal for 1 FPGA clock cycle

    say that this system consist of 2 inputs and 1 output, this system should know when there is signal "no 1" as input and after signal "no 1" end, the system will send out a signal "no 3".

    --- Quote End ---

    But no luck, those error message drive me nuts...

    That is my is my intention, thanks for helping me and sorry for my bad explanation,...

    How about that...?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Shared variables and protected types are meant for testbenching, not synthesis. Protected types were introduced in VHDL 2002.

    Origionally shared variables were meant for direct data transfer between processes. They were declared like a signal but worked like a variable. The problem with this is that because they are updated immediatly, they are not safe. Hence the protected types (though to be honest, you really have the same problems).

    Shared variables (of the old type) can be used to model the correct write-before-read behaviour when implying a dual clocked memory, but quartus doesnt actually create the correct altsync ram (Xilinx does though).

    Basically - keep shared variables and protected types away from quartus - keep them in your favourite simulator.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Just to add - you might get synthesis to work if you remove all of the protected gubbins from the declaration, but it will probably treat the shared variable like a signal.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks Tricky, I have gain more knowledge... :)

    --- Quote Start ---

    basically - keep shared variables and protected types away from quartus - keep them in your favourite simulator.

    --- Quote End ---

    So what is the solution for my problem then? :confused: :confused: :confused:

    And also, how about the error messages? Is that mean that Quartus II doesn't support VHDL 2008 or I just make a mistake somewhere? I still curius about those error messages...

    Thanks...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    hmm,...

    well, I need those two processes to able to write in the (shared) variable or signal, and because signal only can be drived from one process so of course I can't... :D

    or maybe you have an idea regarding my design problem using only a signal? If you really have it, I really appreciate that...

    Thanks... :) :)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Then why not combine the two processes?

    you can use shared variables without the protected typing:

    shared variable s : std_logic;

    then you just write to it like any other variable. At the end of the day though, quartus is still going to give you multiple driver errors.

    I get the feeling you're trying to write this code as code, and not thinking about the underlying hardware, which is essential for hardware design. Without the understanding of the hardware, the VHDL will be meaningless when it comes to synthesis.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Thanks Mr. FvM

    But I think it's specified in VHDL 2008, and I have change the VHDL input to VHDL 2008 in "Setting -> Analysis & Synthesis -> VHDL input". Is Altera Quartus II really support VHDL 2008?

    I need those function to design somekind of clock detector system, here the explanation :

    But no luck, those error message drive me nuts...

    That is my is my intention, thanks for helping me and sorry for my bad explanation,...

    How about that...?

    --- Quote End ---

    Hi,

    according to your drawing the FPGA global clock (24MHz)is running all the time and you would like to detect whether the other clock (6MHz) is on or not. Is that your intention ?

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Tricky =>

    Well, I'm new to FPGA and VHDL so I don't know much about them, I still learning... :)

    --- Quote Start ---

    you can use shared variables without the protected typing:

    shared variable s : std_logic;

    --- Quote End ---

    From what I read from The Designer Guide to VHDL 3rd Edition book, page 589, on the top page, it said that shared variable must be of protected types... how about that?

    --- Quote Start ---

    then you just write to it like any other variable. At the end of the day though, quartus is still going to give you multiple driver errors.

    --- Quote End ---

    But error means can't be synthesize?

    --- Quote Start ---

    I get the feeling you're trying to write this code as code, and not thinking about the underlying hardware, which is essential for hardware design. Without the understanding of the hardware, the VHDL will be meaningless when it comes to synthesis.

    --- Quote End ---

    Well, you got a hit, indeed, I used to play with firmware (C) and computer programming (Java), I need to change my mind set hardware design(FPGA and VHDL)... I found it a bit difficult :D

    Thanks for your advise... I appreciate that... :)

    Pletz =>

    Yes.... It seem you have a good reputation, do you have any idea regarding to my problem?

    Thanks...