Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVHDL Protected type help
Hi everyone,..
I'm new in VHDL and FPGA, sorry for my lame question. Here I have a project, and I thing I will need to use shared variable, here is the code I made : --- Quote Start --- library ieee; use ieee.std_logic_1164.all; -- Shared Function package shared_function is type sh_data is protected procedure reset; procedure set(signal new_data : std_logic); impure function get_data return std_logic; end protected sh_data; end shared_function; package body shared_function is type sh_data is protected body variable data : std_logic; procedure reset is begin data := '0'; end reset; procedure set(signal new_data : std_logic) is begin data := new_data; end procedure; impure function get_data return std_logic is begin return data; end function; end protected body sh_data; end shared_function; --- Quote End --- When I perform "Start Compilation" or "Analyze Current File" in Quartus II Processing menu, I got these error messages : --- Quote Start --- Error (10500): VHDL syntax error at shared_function.vhd(6) near text "protected"; expecting "(", or "access", or "array", or "file", or "range", or "record" Error (10500): VHDL syntax error at shared_function.vhd(10) near text "protected"; expecting ";", or an identifier ("protected" is a reserved keyword), or "package" Error (10523): Ignored construct shared_function at shared_function.vhd(5) due to previous errors Error (10500): VHDL syntax error at shared_function.vhd(14) near text "protected"; expecting "(", or "access", or "array", or "file", or "range", or "record" Error (10500): VHDL syntax error at shared_function.vhd(31) near text "protected"; expecting ";", or an identifier ("protected" is a reserved keyword), or "package" Error: Quartus II Analyze Current File was unsuccessful. 5 errors, 0 warnings Error: Peak virtual memory: 185 megabytes Error: Processing ended: Mon Mar 22 20:38:45 2010 Error: Elapsed time: 00:00:07 Error: Total CPU time (on all processors): 00:00:01 --- Quote End --- I use Altera Quartus II version 9.1 SP1 Subscription Edition and I have changed the VHDL input to VHDL 2008. Really, I don't understand at all, someone help me, please tell me what makes it error, Any kind of help will be greatly appreciated... Thanks :)14 Replies
Altera_ForumTricky and amilcar =>
--- Quote Start --- The basic guide is - dont use shared variables. --- Quote End --- --- Quote Start --- Yeap, do not use shared variables. Sometimes, they just do not work. --- Quote End --- Okay, shared variable should be avoided, thanks for your advice... Mr. FvM => Your solution seem good, okay let me think and try it... Thanks for your help... :) I appreciate that... :)- Altera_Forum
To see, if the 6 MHz clock is toggling, you can use synchronous edge detection. It's easy in this case, because every high or low state of clk6 will be sampled at least once due to the frequency ratio.
signal clk6_s : std_logic; signal clk6_v : std_logic; signal edge_cnt: integer range 0 to 3; process (clk24) begin if rising_edge(clk24) then clk6_s <= clk6; clk6_v <= clk6_s; if (clk6_s XOR clk6_v) = '1' then -- clock edge detected edge_cnt <= 3; elsif edge_cnt > 0 then edge_cnt <= edge_cnt - 1; if edge_cnt = 1 then -- clock just stopped end if; end if; end if; end process; - Altera_Forum
Yeap, do not use shared variables.
Sometimes, they just do not work. - Altera_Forum--- Quote Start --- From what I read from The Designer Guide to VHDL 3rd Edition book, page 589, on the top page, it said that shared variable must be of protected types... how about that? --- Quote End --- This is true, but because it would break a lot of VHDL'93 code (because VHDL 93 allows shared variables the way I showed you) mode compilers just throw a warning rather than an error by default and let you do it (you can change all the pedant settings if you want so it throws an error). The basic guide is - dont use shared variables.
- Altera_Forum
Tricky =>
Well, I'm new to FPGA and VHDL so I don't know much about them, I still learning... :) --- Quote Start --- you can use shared variables without the protected typing: shared variable s : std_logic; --- Quote End --- From what I read from The Designer Guide to VHDL 3rd Edition book, page 589, on the top page, it said that shared variable must be of protected types... how about that? --- Quote Start --- then you just write to it like any other variable. At the end of the day though, quartus is still going to give you multiple driver errors. --- Quote End --- But error means can't be synthesize? --- Quote Start --- I get the feeling you're trying to write this code as code, and not thinking about the underlying hardware, which is essential for hardware design. Without the understanding of the hardware, the VHDL will be meaningless when it comes to synthesis. --- Quote End --- Well, you got a hit, indeed, I used to play with firmware (C) and computer programming (Java), I need to change my mind set hardware design(FPGA and VHDL)... I found it a bit difficult :D Thanks for your advise... I appreciate that... :) Pletz => Yes.... It seem you have a good reputation, do you have any idea regarding to my problem? Thanks... - Altera_Forum--- Quote Start --- Thanks Mr. FvM But I think it's specified in VHDL 2008, and I have change the VHDL input to VHDL 2008 in "Setting -> Analysis & Synthesis -> VHDL input". Is Altera Quartus II really support VHDL 2008? I need those function to design somekind of clock detector system, here the explanation : But no luck, those error message drive me nuts... That is my is my intention, thanks for helping me and sorry for my bad explanation,... How about that...? --- Quote End --- Hi, according to your drawing the FPGA global clock (24MHz)is running all the time and you would like to detect whether the other clock (6MHz) is on or not. Is that your intention ? Kind regards GPK
- Altera_Forum
Then why not combine the two processes?
you can use shared variables without the protected typing: shared variable s : std_logic; then you just write to it like any other variable. At the end of the day though, quartus is still going to give you multiple driver errors. I get the feeling you're trying to write this code as code, and not thinking about the underlying hardware, which is essential for hardware design. Without the understanding of the hardware, the VHDL will be meaningless when it comes to synthesis. - Altera_Forum
hmm,...
well, I need those two processes to able to write in the (shared) variable or signal, and because signal only can be drived from one process so of course I can't... :D or maybe you have an idea regarding my design problem using only a signal? If you really have it, I really appreciate that... Thanks... :) :) - Altera_Forum
Why cant you just use a signal between the two processes?
- Altera_Forum
Thanks Tricky, I have gain more knowledge... :)
--- Quote Start --- basically - keep shared variables and protected types away from quartus - keep them in your favourite simulator. --- Quote End --- So what is the solution for my problem then? :confused: :confused: :confused: And also, how about the error messages? Is that mean that Quartus II doesn't support VHDL 2008 or I just make a mistake somewhere? I still curius about those error messages... Thanks...
